1) Field of the Invention
This invention relates to integrated circuits in general, and more particularly, to integrated circuit memory devices and memory device layouts.
2) Description of the Prior Art
Integrated circuit (IC) memory devices are made up of a plurality of memory cells. In general, one basic memory cell design is duplicated numerous times to form the plurality of cells. The basic cell design may be modified slightly from cell to cell, for example one cell may be a reversed image or complement of an adjacent cell, but the entire memory device can be described according to the basic cell design.
In the case of static random access memory (SRAM) devices, the basic cell is usually in one of two forms, either a six transistor (6T) cell or four transistor/two resistor (4T/2R) cell. Many conventional SRAMs using a 6T configuration have six transistors formed in a bulk semiconductor substrate such as single crystal silicon. This type of SRAM is often fabricated in complementary metal oxide semiconductor (CMOS) technology, four of the transistor being n-channel devices while the remaining two transistors are p-channel devices. The 6T configuration offers several advantages, one being that the device operates at a low level of power. Another advantages is that bulk transistors have good electrical characteristics, including high mobility and low threshold voltages. Moreover, 6T SRAMs are considered to be very stable, having high immunity to cell upsets, such as soft error caused by incident alpha particles. Unfortunately, 6T SRAM cells utilizing transistors formed in a bulk substrate consume a large area because the transistors are formed next to one another in the substrate and are essentially in the same plane. This use of six bulk transistors imposes an unnecessary lower limit on the cell size. Achieving the smallest cell size with the simplest process can reduce the manufacturing costs, increase memory capacity, and increase the device performance without increasing the overall device size.
A reduction in cell area in comparison to the build 6T cell area can be achieved by using a 4T/2R configuration. Cell area is able to be reduced because only four transistors are formed next to one another in a bulk substrate. The four bulk transistors are most often n-channel devices, but may also be p-channel devices enabling the SRAM to be fabricated in either NMOS or PMOS technology. Two resistors that function as load elements are formed above the four bulk transistors, thereby requiring at least one additional conductive layer. A disadvantage with implementing a 4T/2R cell design is that fabrication complexity is increased in comparison to a bulk 6T SRAM design as a result of the additional conductive layer. The additional conductive layer requires at least two more masking steps and also creates a more severe surface topography on the device. As the topography becomes rougher, it becomes more difficult to contact metallization layers, such as bit line metal, to areas within the cell.
Besides an increase in fabrication complexity, 4T/2R SRAM configurations have another disadvantage compared to 6T SRAM configurations. The two load resistors in a 4T/2R SRAM are passive elements whereas the two load transistors in a 6T SRAM are active elements. The 4T/2R SRAM load resistors are passive because the amount of current the resistors can supply to a transistor within the cell is fixed, regardless of the amount to current necessary to store and retain information in a node of the cell. Unfortunately, if the current supplied by a resistor is less than the needed to maintain a logic state, the cell becomes unstable and susceptible to information loss. Load transistors, on the other hand, are able to vary the amount to current being supplied to a node to meet demand, and therefore will be more able to maintain the node's logic state absent any defects in the cell. Yet another disadvantage with the 4T/2R SRAM design is that the 4T/2R SRAM cell requires a relatively high level of power because resistors continuously draw current rather than drawing current only as needed.
A compromise between the advantages and disadvantages of that bulk 6T cell and the 4T/2R cell is the use of a 6 transistor thin-film transistor (6T/TFT) load SRAM cell. As the name suggests, this type of cell utilizes thin-film transistors (TFTs) as load transistors. TFTs, sometimes referred to as polysilicon transistors, are transistors in which both current electrodes and control electrode (i.e., the source, drain, and gate) are each made of a material other than the substrate material, for example polysilicon. The complete 6T/TFT load SRAM cell includes four bulk transistors (2 latch and 2 transfer transistors), usually n-channel devices, and two TFT load transistors which are usually p-channel devices. The two passive load resistors in a 4T/2R cell are replaced in a 6T/TFT load cell by the two TFT load transistors. Thus, the 6T/TFT load SRAM has all the advantages of having active load elements.
FIG. 1 shows an electrical schematic of a 6 transistor static random access memory device (6T SRAM). Transistors labeled T1 and T2 are transfer transistors, T3 and T4 are latch transistors, and T5 and T6 are load transistors. A current electrode 30, 32 of the load transistors is connected to a bit line 46, 48.
Although thin film transistors (TFTs) typically do not have electrical characteristics as good as those of bulk transistors, the savings from cheaper fabrication costs are considered by many to outweigh electrical disadvantages. The size of a 6T/TFT load SRAM cell is comparable to that of a 4T/2R cell, yet the use of two load transistors results in a much more stable device than a cell which employs resistors. Power consumption of a 6T/TFT load SRAM is higher than that of the bulk 6T device, but considerable lower than that of the 4T/2R device.
Overall, the 6T/TFT load SRAM is considered to have better electrical performance than a 4T/2R SRAM while maintaining a favorable sized cell. However, there is a need to reduce cell size further to achieve increased memory capacity without an increase in device size. Therefore, a need exists for an improved integrated circuit memory device, and more specifically for an improved integrated circuit memory device and a structural layout thereof in which cell size is reduced over existing memory cells.
Silvan, U.S. Pat. No. 5,198,683 discloses a 6T/TFT SRAM cell which contains two vertical load thin film transistors (TFTs). Vertical TFTs are similar to standard TFTs in that both the source, drain, and gate are composed of a material other than the substrate, sometimes polysilicon. In a vertical TFTs, the transistor is formed in a trench in the substrate. Four of five interconnects associated with each storage node are defined by trenches. The use of vertical TFTs and consolidation of the contacts in the trench allows for a substantial reduction in cell size. The reduction is attributable to the small size of vertical TFT as compared to more common planar transistors. Also, the transistor interconnects are confined to a small area within the cell which is defined by a minimum feature size. However, the manufacturing process for vertical TFTs is complicated and expensive because vertical TFT are formed from four layers of polysilicon and trench construction is complex.